The present invention relates in general to memory management, and more specifically, to utilizing dedicated READ and WRITE ports to READ and WRITE from/to memory.
Computer systems, processors, caches, I/O device and other devices in the computer architecture access data in memory using one or more memory controllers. The memory controllers manage the movement of data to and from memory, for example, a dynamic random access memory (DRAM).
The memory can be a generation of double data rate (DDR) memory, for example, DDR3, DDR4, DDR5, etc. A series of memory circuits that make up the DDR memory can be used to create a dual in-line memory module (DIMM).